1. Field of the Invention
The present invention relates to a semiconductor memory device which generates, by means of a replica circuit comprising a replica cell whose structure is identical to that of a memory cell which is contained in a memory array, a start-up timing signal for a sense amplifier circuit, and relates to the circuit layout of a dummy cell.
2. Background Art
There are a number of methods for a conventional semiconductor memory device to generate a timing signal for a sense amplifier which amplifies data read from a memory cell and ensures that the timing of reading from a memory cell follows changes attributable to a process, a voltage, etc. Among these is a method of generating a timing signal using a replica circuit (See Patent Literature 1 and Patent Literature 2 for instance.) This method will now be described.
FIG. 1 is a functional block diagram which shows one example of the structure of a semiconductor memory device which uses a replica circuit. In FIG. 1, the semiconductor memory device comprises a memory control circuit 100, SRAM memory cells 101, a memory array 102 formed by the plural SRAM memory cells, a sense amplifier circuit 103 which amplifies and outputs signals transmitted on bit lines BL and NBL which are connected with the memory cells 101, a row decoder 104 which is connected with the memory array 102, replica cells 105, a replica circuit 106 comprising the replica cells 105, a replica word line 107 which sends a signal to the replica circuit 106, a replica bit line 108 which is connected with the replica cells 105, dummy cells 109 which are connected with the replica bit line 108, and a sense amplifier control circuit 110 which is connected with the replica bit line 108 and sends a sense amplifier control signal SAE to the sense amplifier circuit 103.
As shown in FIG. 1, the memory cells 101 are connected in the row direction respectively with word lines WL0 through WLx which are output signal lines from the row decoder 104, and connected in the column direction with common bit lines BL and NBL.
FIG. 2 is a circuitry diagram of the internal structure of the memory cell 101 which is shown in FIG. 1. In FIG. 2, the memory cell 101 is formed by an N-type transistor NA1 whose gate is connected with the word line WLx and whose source is connected with the bit line BL, an N-type transistor NA2 whose gate is connected with the word line WLx and whose source is connected with the bit line NBL, a P-type transistor PL1 whose source receives a power source voltage VDD and whose drain is connected with the drain of the N-type transistor NA1, an N-type transistor ND1 whose gate is connected with the gate of the P-type transistor PL1, whose drain is connected with the drain of the P-type transistor PL1 and whose source is connected with a ground potential VSS, a P-type transistor PL2 whose gate is connected with the drain of the N-type transistor NA1, whose source receives the power source voltage VDD and whose drain is connected with the drain of the N-type transistor NA2 and the gate of the P-type transistor PL1, and an N-type transistor ND2 whose gate is connected with the gate of the P-type transistor PL2, whose drain is connected with the drain of the P-type transistor PL2 and whose source is connected with the ground potential VSS.
The P-type transistor PL1 and the N-type transistor ND1 form a first inverter, the P-type transistor PL2 and the N-type transistor ND2 form a second inverter, and an input terminal and an output terminal of the first inverter are connected respectively with an output terminal and an input terminal of the second inverter, thereby forming a latch circuit.
FIG. 3 is a circuitry diagram which shows the internal structure of the replica cell 105 which is shown in FIG. 1. In FIG. 3, transistors forming the replica cell 105 have the same sizes as the transistors forming the memory cell 101 which is shown in FIG. 2. In the latch circuit included in the replica cell 105, the drain and the source of the P-type transistor PL2 are short-circuited, and the output level of the second inverter formed by the P-type transistor PL2 and the N-type transistor ND2 is fixed at the High level. Meanwhile, the gate of the N-type transistor NA1 is connected with the replica word line REPWL 107.
FIG. 4 is a circuitry diagram of the internal structure of the dummy cell 109A which is shown in FIG. 1. In FIG. 4, transistors forming the dummy cell 109A have the same sizes as the transistors forming the memory cell 11 which is shown in FIG. 2. In addition, the gate of the N-type transistor NA1 is fixed at the Low level.
An operation of the conventional semiconductor memory device having the structure above will now be described. First, one of the word lines WL0 through WLx which are the output signal lines from the row decoder 104 is selected, data in the memory cell 101 are read to the bit lines BL and NBL. The bit lines BL and NBL and the replica bit line REPBL 108 are pre-charged to the High level and become floating upon selection from among the word lines WL0 through WLx. The multiple bit lines BL and the multiple bit lines NBL are provided, and plural pieces of data are read to the associated bit lines BL and NBL.
At about the same timing as the timing of selecting from among the word lines WL0 through WLx, the replica word line REPWL 107 which is an output signal line from the control circuit 100 is driven. This makes the transistors of the n replica cells 105 transit the signal level on the replica bit line REPBL 108 from the High level to the Low level at a speed which is n times as fast as that of the memory cells 101. The sense amplifier control circuit 110 then detects the signal level on the replica bit line REPBL 108 and generates the sense amplifier control signal SAE. As the sense amplifier circuit 103 receives the sense amplifier control signal SAE, and therefore amplifies the data on the bit lines BL and NBL.
Where the power source voltage VDD is 1.2 V for example, if one wishes to start up the sense amplifier circuit 103 while reading of data from each memory cell 101 to the associated bit lines BL and NBL accompanies a potential difference of 100 mV, one may decide that the number n of the replica cells 105 to choose is 6, thereby ensuring that the signal level on the replica bit line REPBL 108 would have transmitted 600 mV, that is, down to half the power source voltage VDD at any desired timing that the sense amplifier is supposed to start up, and thereby achieving a benefit that it is possible to generate the sense amplifier control signal SAE at simple CMOS gates without using a complicated potential detection circuit.
Patent Literature 1: Japanese Patent Application Laid-Open Gazette No. H9-259589 (page 4, FIG. 7)
Patent Literature 2: Japanese Patent Application Laid-Open Gazette No. 2003-36678 (pages 5–6, FIGS. 5–6)
However, in the structure above of this semiconductor memory device, internal nodes of the dummy cell 109 are not fixed. The potential at the drain of the N-type transistor NA1 shown in FIG. 4 could therefore change to the Low level. When this occurs, due to a leak current, the N-type transistor NA1 makes the replica bit line REPBL 108 more quickly transit from the High level to the Low level. This shortens the time given to the sense amplifier control circuit 110 to detect the transition of the replica bit line REPBL 108, making it impossible to obtain the desired timing. In some situations, the sense amplifier control signal SAE could come too early and cause the sense amplifier circuit 103 to malfunction.
Meanwhile, in the semiconductor memory device according to Patent Literature 2, the statuses of the dummy cells are fixed such that of paired nodes of the dummy cells, the ones closer to the replica bit line which is driven to the Low level will remain at the High level, for the purpose of preventing a leak current from the dummy cells from quickening the timing at which the replica bit line is driven to the Low level.
However, upon leakage at the access transistors between the dummy cells which are fixed to the High level and the replica bit line which is driven to the Low level, namely, the N-type transistors NA1 shown in FIG. 4, the structure above could block the replica bit line from switching to the Low level, thereby giving rise to an unnecessary current or resulting in failure to achieve the desired timing.